Thanks to all who responded. I have now sent an email to pmade...

Thanks to all who responded. I have now sent an email to pmade (at) brainchipinc dot com to ask for clarity on the resource utilization for the milestone and Akida (and the email didn't bounce back). On the off chance that I get a response, I will share any information I receive.

To comment on a few of the responses:

@glutenfree
The suggestion that the neural and synaptic count is in terms of comparison to sigmoid neurons (4997:1 ratio) would take us from 1.2 million to 240 neurons, and that actually seems like a feasible implementation from my estimated resource utilization. That said, it seems very odd that they would tell us about the functional blocks in their neuron and then give the Akida specifications in terms of the resources needed by a different kind of design to achieve the same performance. I also think there's a lot more work to be done to justify that ratio. The referenced paper gives 4997 as the number of extra "computation nodes" for an "element distinctiveness function" with 10,000 synaptic inputs in a section titled "Spiking Neurons have more Computational Power than Sigmoidal Neurons". This is going beyond my expertise, but if they're saying that a spiking neuron counts as a single computation node, then the 4997:1 ratio in computational power is a valid claim when there are 10,000 synapses per neuron. But when there are fewer synapses (suppose Akida has 256 synapses per neuron, as with SNAP64), the ratio drops to 126:1. The computational ratio is always roughly half the number of synapse inputs per neuron. So that multiplier would almost certainly be completely misleading if applied to Akida.

@jtardif999
I definitely am not a neural network expert, but I am familiar with digital logic. The literature has repeatedly stated that the IP is constructed from pure CMOS logic, and everything I've seen confirms this. That entails the use of transistors to construct flip-flops and logic gates. In addition to the block diagram they have provided for the neuron, there are other statements about the size of the data stream: 18 bits for the synapse, 22 for the dendrite, and 24 for the soma. Combine this with the other registers and logic identified in the architecture and it's effectively impossible that the numbers they provided apply to the neuron and synapse blocks as presented for their design.

I'm also quite certain that SNAP64 only had 64 neurons with 256 synapses each. The FPGAs couldn't support 64k neurons, and the abstract for Peter's talk at the MPSOC forum states 64 neurons with 256 synapses each. I interpret the quote of 65536 neurons as being with regard to the architecture's foreseeable capacity rather than it's actual implementation in the SNAP64 instance. Or it might also be a mistake, where the synapse count was given as a neuron count. Regardless, given my resource estimates, I'm still very skeptical that they can put anything close to 64k neurons on a single chip any time soon, unless the synapse per neuron is much lower than their statements have indicated thus far. So now that I read the quote again and see that it was directly attributed to a written text from Peter that could be copied and pasted, I'm feeling a bit uneasy.

@cyberworks
I understand the need for IP protection, but they could easily address these concerns without revealing anything worthwhile. Giving a rough transistor count for the implementation tells you far less than is already disclosed in the literature.

@managarm
Agree that they were up-front about the use of the Xilinx FPGA. I just thought it odd that they felt the need to remove any indication that the board itself came from Alpha Data. The Brainchip image intentionally blurs the silkscreen that identifies the board (the fuzzy blank area above the shield). It's a marketing gimmick, so this is the least of my concerns, but it is a curiosity.

Thanks again to all.