Technology due diligence

I discovered Brainchip from the articles on EETimes in September 2018 and after doing a little bit of research I decided that they appeared to be legit and made a small investment. With the stock now on my radar, the recent performance has led me to dig deeper; to figure out whether I was duped or if this is an opportunity to buy more. So I'm interested in hearing your thoughts on some observations I've put together after doing a bit more research. This appears to be the only place where people are regularly discussing Brainchip. For background, I am an engineer in the US who is familiar with FPGAs, but I'm not an expert in neural networks.

Observation #1 - Milestone 2 in October 2015 implemented the SNAP64 architecture on a Dini Group board with multiple Xilinx Virtex-7 2000T FPGAs. This board is probably the DNV7F4A containing four chips. This provides a total of nearly 8 million logic cells at full utilization (where each logic cell is the equivalent of a 4-input look-up table and a flip-flop). We're told that SNAP64 implements 64 neurons with 256 synapses each. If we assume a generous 90% utilization on the FPGAs for just the SNN fabric, this equates to about 112500 logic cells per neuron. Each synapse has its own temporal integrator, STDP function, a neurotransmitter function, a neuromodulator function, a strength function, a slope function and a duration function. If we assume something like 10000 logic cells for the post-synaptic logic (delays, dendrite integration, soma integration, and spike shaping) then we're left with about 400 logic cells per synapse. Note that this is ignoring the "connectome" (the logic to route the trained network according to the training results) and all other supporting logic. These certainly chew up a fair bit of space and overall makes the 90% utilization a very optimistic estimate. So, while it seems plausible to implement this on the DNV7F4A board, I feel like I have to be very generous and optimistic to make it work. It would be illuminating to get details on the utilization for this implementation.

Observation #2 - The Akida NSoC is claimed to support 1.2 million neurons and 10 billion synapses (though this is sometimes qualified as an "effective" quantity), and has been given a price target of $10 - $15 (in volume). If this is literal, it's ludicrous. While it is certainly true that there are a lot of gains to be made moving from an FPGA to an ASIC, I can't see how they can produce an ASIC with 75000 times the number of neurons compared to the implementation achieved on a single Virtex-7 2000T FPGA (assuming 16 neurons per FPGA in the milestone, and ignoring that larger network should have more synapses per neuron). They're using "pure CMOS logic", so there's no special analog circuit that replaces a bunch of transistors. The largest ASIC (per Wikipedia) is 23.6 billion transistors (the G2C IPU). Even if there were only 3 transistors per synapse, Akida would become the chip with the most transistors. If we take these numbers literally, we're talking about TRILLIONS of transistors. Furthermore, it seems impossible that this could cost anything close to $10 - $15 and consume less than 1W (with a 28nm process, no less). The chip would be substantially far more complex than the 2000T FPGA, which costs thousands of dollars and consumes dozens of watts for a design like this. The numbers have to be wrong somewhere. The only way I can make sense of this is if the 1.2M neurons and 10B synapses are not literal and "effectively" represent what would be required by implementations in traditional processor technology to achieve equivalent throughput. This is by far the observation that I'm struggling with the most, and I would really like to see an explanation.

Observation #3 - The Brainchip Accelerator is clearly an off-the-shelf board (Alpha Data ADM-PCIE-8K5) with a custom FPGA program implementing the SNN. The FPGA on this board provides 1.45 million logic cells. Per the estimates from Milestone 2 above it would support no more than 13 neurons with 256 synapses each - but there are probably fewer synapses if there are also fewer total neurons, so it might be something more like 24 neurons with 128 synapses each. What's also interesting is that the off-the-shelf nature of the hardware is not disclosed anywhere and the branding on the board is intentionally erased in the images from Brainchip. There's nothing wrong with buying an off-the-shelf board, loading a custom image to it, and reselling it as something else, so I don't know why they would hide this. It's also possible that the existence of this board could be seen as a testament to the scalability of the architecture in that they were able to get something functional by scaling down from the design that was used in Milestone 2.

Finally, though these observations are generally negative, I don't want to leave the impression that I think this company is a sham. In this process I've also discovered a long history of progress. I like to think that the neuron architecture makes sense. There's strong evidence that many personnel are well qualified, and of collaborations with legitimate professionals and researchers. As much as the observations above bother me, I also can't dismiss all the signs that there is a real technology being developed here that is a game changer if they can see it through.So does anybody have any thoughts on these observations?