How long for rigorous testing ?

ACCESS SPEED ?

CYCLING ENDURANCE ?

RESOLUTION ?

DATA RETENTION ?

Should be at customs now getting bag checked.

Hopefully already inserted in multiple IMEC Megabit memory vehicles and testing many at once.

Compared to transferring the core chip design from lab to fab, integrating this design withIMEC’s megabit memory vehicle should be relatively straightforward given IMEC has donethis numerous times and the platform is a standard design.It will require some rigorous testing, though, specifically for yield, speed, endurance andretention. With all memory cells in a memory chip, they are accessible and testable atstandard memory speeds – rather than individually as is the case in 4DS’ lab setting.