Thanks for your reply

Here's mine in two parts:

PART I

Markets initially:
WBT emedded memory -mass produced small devices, IoT devices
4DS high-densitty, high-volume memory -data centres, cloud environments

In response to some of your points:

"Technology"

WBT targeting 28nm (20% bettter performance)

"Small filament may result in good integration with logic functions in SoC’s

The small diameter of the filament (5nm to 7nm) in the SiOx layer potentially allows forsubstantial downscaling of the memory cell and surrounding circuitry. Given that today’sleading-edge resolutions of logic chips, such as CPU’s, measure less than 20nm, downscalingof SiOx ReRAM cells to, say, 20nm-28nm, may more easily enable integration of thistechnology into SoC’s and devices with embedded memory.

Put differently, the smaller the size of the memory cells, the closer they can be positionedto the logic elements on the chip in SoC’s. This increases the chip speed, reduces powerconsumption and enables further device shrink.

Smaller feature sizes should also allow future SiOx ReRAM cells to be stacked in 3D structures,similar to 3D NAND Flash today, to create higher bit densities at lower costs.

However, the crucial part in scaling down SiOx ReRAM cells below 30nm, and potentially evenfurther towards 20nm, will be WBT’s ability to scale down the chip circuitry around the actualmemory cell. As the cell is scaled down, this surrounding circuitry will still need to be able toconduct the same voltages needed to switch the memory cell. If this circuitry gets too small,there may be a risk that the currents get too high and the circuitry will fail.

This issue will only come into play once WBT starts development work to scale its technologydown below 40nm, which is not an immediate priority at the moment."

Source: https://www.tmt-analytics.com.au/uploads/7/7/9/5/77956374/wbt_company_report_191017.pdf

Now read the YELLOW bit below:

Progress with 28nm

"successful endurance results of its ReRAMcells as a key step towards moving to 300mm wafers at 28nm. The ReRAM cells demonstrated stable voltage levelsand endurance, at levels competitive to production non-volatile memories.

Weebit and its partner Leti, the French research institute recognised as a global leader in the field of microelectronics, performed the tests which demonstrated Array-level endurance above 100,000 cycles, on par withexpectation in the storage memory market, and a significant improvement over flash memories. In addition, Weebitensured the SiOx ReRAM layer will be compatible with different tools and technologies used by different productionfabs, which is crucial for transferring the Weebit technology to different commercial manufacturers.

Final characterisation will continue over coming weeks [Newsflow!] on array performance and extended endurance and retentionin preparation for the migration to 300mm wafers at 28nm."

4DS targeting 40nm

Progress with 40nm

"has fabricated functional 300mm wafers on the same multi-million dollar state-of-the-art production equipment usedby high volume manufacturers of memory.

As previously reported the Board believes 4DS remains on track and is confident that detailed testing and analysisover the balance of Q1 2019 at 4DS’ facilities, will provide invaluable data to refine the fabrication processesrequired to produce a megabit test chip during 2019."

WBT - SiOx- Silicon Oxide (SiOx)

• Materials: Dirt (sand) cheap;
• Fabrication: No major costs for modifying / calibrating fabrication processes, as silicon oxide has been used by the industry for 60 years

4DS - MOHJO - Metal Oxide Hetero Junction Operation

• Materials: Rare earth materials, costly;
• Fabrication: Expensive re-tooling and calibration required by chip manufacturers

Next-Gen Memory Ramping Up

"In fact, it has been a struggle to bring many new memory types into mass production. These memories rely on exotic materials and switching mechanisms, making them difficult to fabricate and/or operate in the field. They are also expensive."

"Still, it’s unlikely that the new memories will displace DRAM, flash or SRAM, at least for now.

It all boils down to performance, density and cost. For example, the cell size for a given memory equals the feature (F) size times four square. The smallest cell size is 4F². The latest 3D NAND devices incorporate four bits per cell (QLC), which in theory translates into a cell size of 1F².

“If you want to displace NAND, you have to be cheaper than 1F². As far as I know, we won’t see that in our lifetime,” said Ed Doller, a memory veteran and board member at Nantero, a developer of carbon nanotube RAMs.

To displace DRAM, a new memory type must be cheaper as well as having an entire infrastructure around it, such as a DRAM-compatible interface and a controller."

Source: https://semiengineering.com/next-gen-memory-ramping-up/


WBT: 

"WBT’s technology has several key advantages over certain other emergingmemory technologies. SiOx has been used in semiconductormanufacturing for decades and is a very well-understood material that thesemiconductor industry knows how to process. Therefore, SiOx ReRAM isCMOS compatible and should have a relatively short time-to-market oncelicensed to a semiconductor manufacturer.

The technology is versatile and suitable for use in both embeddedmemory, such as in IoT devices, as well as Systems on a Chip (SoC).Furthermore, we believe Storage Class Memory (SCM) will be a majorapplication area for SiOx ReRAM as well."

"Significant achievements to date

WBT has already built Kb arrays of memory cells at 300nm and has demonstrated fast writespeeds (100x to 1,000x faster than NAND Flash), low energy consumption, narrow resistivitydistribution across the arrays and zero cell-to-cell interference at this resolution.

The achievement of narrow resistivity distribution across the arrays is particularly importantas it shows uniformity across a large number of cells, which is crucial in validating the abilityto scale up the technology to Mb [tick!] and, eventually, Gb arrays.

Additionally, the achievement of Kb arrays in itself is very significant as this implies WBTshould be able to build Mb [tick!] and Gb arrays as well, given that these simply comprise of manyindividual Kb arrays."

Source: https://www.tmt-analytics.com.au/uploads/7/7/9/5/77956374/wbt_company_report_191017.pdf


Why Intel may still be searching for a solution:

In reality, though, 3D XPoint has been delayed and failed to live up to those specs. “We know much of that was over-hyped in reality,” said Mark Webb, the principal at MKW Ventures, a consulting firm. “The reality is different, but it’s still pretty amazing. 3D XPoint will have more revenue than all other new nonvolatile memories combined.”The technology is fast, but it isn’t 1,000 times faster than NAND. “It also has a much higher cost than NAND,” Webb said. “It’s not a DRAM replacement. It complements DRAM.”

Source: https://semiengineering.com/next-gen-memory-ramping-up/

Opinion only, dyor etc