Ann: imec Collaboration Update, page-53

spot on.

Given the lessons learned on it1 then I would expect:
1: they get a functional wafer produced (bare minimum) = tick
2: they get a good success rate regarding low defects, electrical functionality (superior operating cost efficiency), logic functionality, read-write speeds desired, retention-endurance nicely between DRAM and NAND Flash as desired

= tick pending

3: identify additional tweaks for debuging before = will follow 2 naturally
4: moving on to megabit chip production = dependent on step 2/3

happy days.