Ha, fair enough, my take on my own explanation is... the patent includes two way communication between the controller and array and also restrictions of movement of inactive arrays. Does that make sense?Curious that it was granted a few days ago as these are so pertinent to the functional working of the chip right now.
Interesting that the original application of the patent was 2013. I have little understanding of the patent process, seems initial application only needs the subject and not detailed description. Also apparently 18 months is the normal lead time.
I understand diddly squat, but posted because I'm curious if anyone can illucidate.